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Freescale Semiconductor /MKL28T7_CORE1 /TRGMUX0 /TRGMUX_LPIT0

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Interpret as TRGMUX_LPIT0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SEL00SEL10SEL20 (0)SEL30 (0)LK

LK=0, SEL3=0

Description

TRGMUX TRGCFG Register

Fields

SEL0

Trigger MUX Input 0 Source Select
SEL1

Trigger MUX Input 1 Source Select
SEL2

Trigger MUX Input 2 Source Select
SEL3

Trigger MUX Input 3 Source Select

0 (0): Trigger function is disabled.

1 (1): Port pin trigger input is selected.

2 (2): FlexIO Timer 0 input is selected.

3 (3): FlexIO Timer 1 input is selected.

4 (4): FlexIO Timer 2 input is selected.

5 (5): FlexIO Timer 3 input is selected.

6 (6): FlexIO Timer 4 input is selected.

7 (7): FlexIO Timer 5 input is selected.

8 (8): FlexIO Timer 6 input is selected.

9 (9): FlexIO Timer 7 input is selected.

10 (10): TPM0 Overflow is selected

11 (11): TPM0 Channel 0 is selected

12 (12): TPM0 Channel 1 is selected

13 (13): TPM1 Overflow is selected

14 (14): TPM1 Channel 0 is selected

15 (15): TPM1 Channel 1 is selected

16 (16): LPIT1 Channel 0 is selected

17 (17): LPIT1 Channel 1 is selected

18 (18): LPIT1 Channel 2 is selected

19 (19): LPIT1 Channel 3 is selected

20 (20): LPUART0 RX Data is selected.

21 (21): LPUART0 TX Data is selected.

22 (22): LPUART0 RX Idle is selected.

23 (23): LPUART1 RX Data is selected.

24 (24): LPUART1 TX Data is selected.

25 (25): LPUART1 RX Idle is selected.

26 (26): LPI2C0 Master STOP is selected.

27 (27): LPI2C0 Slave STOP is selected.

28 (28): LPI2C1 Master STOP is selected.

29 (29): LPI2C1 Slave STOP is selected.

30 (30): LPSPI0 Frame is selected.

31 (31): LPSPI0 RX data is selected.

32 (32): LPSPI1 Frame is selected.

33 (33): LPSPI1 RX data is selected.

34 (34): RTC Seconds Counter is selected.

35 (35): RTC Alarm is selected.

36 (36): LPTMR0 Trigger is selected.

37 (37): LPTMR1 Trigger is selected.

38 (38): CMP0 Output is selected.

39 (39): CMP1 Output is selected.

40 (40): ADC0 Conversion A Complete is selected.

41 (41): ADC0 Conversion B Complete is selected.

42 (42): Port A Pin Trigger is selected.

43 (43): Port B Pin Trigger is selected.

44 (44): Port C Pin Trigger is selected.

45 (45): Port D Pin Trigger is selected.

46 (46): Port E Pin Trigger is selected.

47 (47): TPM2 Overflow selected.

48 (48): TPM2 Channel 0 is selected.

49 (49): TPM2 Channel 1 is selected.

50 (50): LPIT0 Channel 0 is selected.

51 (51): LPIT0 Channel 1 is selected.

52 (52): LPIT0 Channel 2 is selected.

53 (53): LPIT0 Channel 3 is selected.

54 (54): USB Start-of-Frame is selected.

55 (55): LPUART2 RX Data is selected.

56 (56): LPUART2 TX Data is selected.

57 (57): LPUART2 RX Idle is selected.

58 (58): LPI2C2 Master STOP is selected.

59 (59): LPI2C2 Slave STOP is selected.

60 (60): LPSPI2 Frame is selected.

61 (61): LPSPI2 RX Data is selected.

62 (62): SAI TX Frame Sync selected.

63 (63): SAI RX Frame Sync is selected.
LK

Enable

0 (0): Register can be written.

1 (1): Register cannot be written until the next system Reset.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data